A non-inverting BICMOS tristate output buffer circuit according to the related patent application noted above is illustrated in FIG. 1. The BICMOS output buffer circuit delivers output signals of high and low potential levels H,L at the output V.sub.OUT in response to data signals at the input V.sub.IN. Darlington bipolar output pullup transistors Q24,Q22 source current to the output V.sub.OUT from the high potential output supply rail V.sub.CCN through diode SD1 and resistor R6 coupled to the collector node of bipolar output pullup transistor Q22. High current drive bipolar output pulldown transistor Q44 composed of parallel transistor elements Q44A and Q44B sinks current from the output V.sub.OUT to the low potential output ground rail GNDN.
On the pullup side of the output buffer circuit a CMOS pullup driver circuit is coupled to the output pullup transistors. The CMOS pullup driver circuit is composed of a first pullup predriver input inverter stage Q15,Q14 coupled to the input V.sub.IN, and a second pullup driver inverter stage Q21A,Q20 coupled to the first inverter stage Q15,Q14 at an intermediate node n1. The second inverter stage Q21A,Q20 is coupled to the base nodes of bipolar output pullup transistors Q24,Q22. With a high potential level data signal H at the input V.sub.IN, the second pullup driver inverter stage PMOS transistor Q21A provides base drive current to bipolar transistor Q24. Bipolar transistor Q24 in turn sources amplified base drive current from output supply rail V.sub.CCN to bipolar output pullup transistor Q22 through Schottky diode SD1 and resistor R5.
For a low potential level data signal L at the input V.sub.IN, the second pullup driver inverter stage NMOS transistor Q20 discharges the base of bipolar output pullup transistors Q24,Q22. The discharge path from the base node of output pullup transistor Q22 contains breakdown protection voltage drop components in the form of Schottky diodes SD12 and SD11. Diodes SD11 and SD12 add sufficient voltage difference to prevent breakdown current flow back from the output V.sub.OUT through the base/emitter junction of output pullup transistor Q22. This breakdown protection prevents current flow through NMOS transistor Q20 during the high impedance third state at the output. In the tristate mode of operation of the BICMOS output buffer circuit hereafter described, a high potential level signal at the output V.sub.OUT from another output buffer circuit on a common bus might otherwise cause breakdown current to flow in a discharge path through Q22 and Q20.
On the pulldown side of the BICMOS output buffer circuit, a first pulldown predriver input inverter stage Q11,Q10 is coupled to the input V.sub.IN. A second pulldown driver stage Q60,Q9A is coupled to the base node of the bipolar output pulldown transistor Q44. The pulldown driver stage includes an NMOS pulldown driver transistor Q60 having a control gate node coupled to a common node n2 of the pulldown predriver input stage Q11,Q10. The pulldown driver transistor Q60 is coupled for sourcing current from the high potential level power rail V.sub.CCQ through diode SD3 and limiting resistor R4 to the base node of bipolar output pulldown transistor Q44. Transistor Q60 is an effective "phase splitter" operating bipolar output pulldown transistor Q44 out of phase with bipolar output pullup transistor Q22.
The pulldown driver stage also includes a Miller Killer transistor Q9A coupled for sinking parasitic Miller capacitance current from the base node of bipolar pulldown transistor Q44 to the output ground GNDN. A Miller Killer predriver stage Q40,Q41 is coupled between the common node n2 of the pulldown predriver input stage Q11,Q10 and the control gate node of the MK transistor Q9A. The small current conducting MK transistor Q9A and MK predriver stage transistors Q40,Q41 are constructed with small channel width dimensions for fast switching operation. The operation of MK transistor Q9A is sufficiently fast so that it operates as an ACMK during HL transitions at the output V.sub.OUT as well as a DCMK transistor after switching during steady state high H at the output V.sub.OUT.
An accelerating feedback diode SD4 is coupled between the output V.sub.OUT and the drain node of pulldown driver transistor Q60. Discharge current from the output V.sub.OUT is therefore fed back through the primary current path of NMOS pulldown driver transistor Q60 for accelerating turn on of the bipolar output pulldown transistor Q44 during transition from high to low potential level HL at the output.
The BICMOS output buffer circuit of FIG. 1 and FIG. 4 also incorporates a tristate enable circuit having complementary tristate enable signal inputs E and EB. A CMOS pullup tristate enable stage Q16,Q13 is coupled in a NAND gate coupling with the pullup predriver input stage Q15,Q14 in the first data signal path. Thus, the PMOS transistors Q16,Q15 are coupled in parallel and the NMOS transistors Q14,Q13 are coupled in series. The NAND gate inputs are the data input V.sub.IN and the enable signal input E.
A pulldown tristate enable stage Q12,Q9 is coupled in a NOR gate coupling with the input pulldown predriver stage Q11,Q10 in the second data signal path. Thus, PMOS transistors Q12,Q11 are coupled in series and NMOS transistors Q10,Q9 are coupled in parallel. The NOR gate inputs are the data input V.sub.IN and the complementary enable signal input EB.
MOS, bipolar, and BICMOS integrated circuit output buffers and devices turn on the pulldown transistor element for discharging the output load capacitance and for sinking current from the output to external ground during transition from high to low potential at the output. The surge or acceleration of charge develops a voltage across the output ground lead inductance proportional to L di/dt resulting in a positive ground rise in potential or ground bounce in what should be a statically low output This output ground bounce may typically be in the order of 0.5 to 2.5 volts above the external ground 0 volts for circuits with a power source V.sub.CC operating at 5 volts. The maximum or "peak" ground bounce output noise which this causes at the output V.sub.OUT is referred to herein as V.sub.OLP.
Deceleration of the initial surge of sinking current charge through the pulldown transistor element develops another voltage across the output ground lead inductance causing a negative ground voltage undershoot of potential in the output ground lead having opposite polarity from the ground bounce. The absolute value of the output undershoot negative spike may be greater than the positive ground bounce spike. The maximum "valley" or minimum peak of the ground undershoot output noise which this causes at the output V.sub.OUT is referred to herein as V.sub.OLV.
The disruptive effects of this noise from the output ground and supply leads at the output V.sub.OUT include interference with other low or quiet outputs on a common bus. The present invention is particularly directed to reducing the problem of disruption of quiet outputs on a common bus. For example, an active low output V.sub.OUT of an octal buffer line driver on a common bus may experience a peak output noise voltage rise V.sub.OLP causing a false high signal. These problems associated with output ground and supply noise are of increased concern as integrated circuits switch higher currents at higher speeds.
Reduction of switching induced noise in an all-CMOS transistor output buffer circuit is described in the Jeffrey B. Davis U.S. Pat. No. 4,961,010. The Davis CMOS transistor output buffer circuit 40 is illustrated in FIG. 2. Multiple output buffers of this type may be incorporated, for example, as output buffers in an octal buffer line driver. The pulldown transistor element is provided by the relatively large current conducting NMOS transistor N3. The pullup transistor element is provided by relatively large current PMOS transistor element P3. Output buffer 40 is a non-inverting tristate output device, and data signals propagate from the input V.sub.IN to the output V.sub.OUT. The tristate output enable and disable signals are applied at the OE terminal input.
A data signal at the input V.sub.IN passes through two inverting current amplification stages 12, 14 and then is applied at the same polarity as an input to NAND gate 15 and NOR gate 16. NAND gate 15 drives pullup transistor element P3. NOR gate 16 drives the pulldown transistor element N3. The second input to each of the gates 15, 16 is derived from the OEB terminal input.
The tristate enable signal OEB is applied in inverted polarity from output enable signal OE at the tristate OEB terminal. This tristate signal passes through first and second inverting current amplification stages 18, 20 and is applied at the same polarity as the OEB signal to an input of NOR gate 16. The tristate signal also passes through first and second inverting stages of current amplification 18, 20 and a third inverter stage 22 before it is applied to the input of NAND gate 15. The tristate signal applied to the input of NAND gate 15 is thus of opposite polarity from the OEB signal and is in phase with output enable signal OE.
The output buffer circuit 40 according to U.S. Pat. No. 4,961,010 includes a relatively small current conducting secondary pullup transistor element, PMOS transistor P1. A relatively small current secondary pulldown transistor element is provided by NMOS transistor N1. The ratio of current carrying capacities of the primary pulldown transistor element N3 to the secondary pulldown transistor element N1 is preferably at least 4 to 1 or greater and typically in the range of 4/1 to 7/1. The same ratio of current carrying capacities is used for the primary to secondary pullup transistor elements.
Referring to FIG. 2, a time constant delay between early turn on of the secondary pulldown transistor element N1 and the primary pulldown transistor element N3 is provided by a separate resistor or resistance element R1 coupled between the control terminal leads of the secondary and primary pulldown transistor elements N1 and N3. Resistor R1 cooperates with the inherent input gate oxide capacitance of pulldown transistor N3 to form an RC network with a time constant delay of for example 1 to 5 ns.
Similarly on the supply side, separate resistor element R2 is coupled between the control terminal leads or gates of secondary and primary pullup transistor elements P1 and P3. Resistor R2 is typically selected to have a value cooperating with the larger output capacitance of primary pullup element P3 to provide the desired RC time constant delay between the early turn on of secondary pullup transistor P1 and the later turn on of primary pullup transistor element P3.
A feature of this circuit described in U.S. Pat. No. 4,961,010 is that the early turn on of a small current carrying capacity secondary pulldown transistor element initiates pulldown at the output and sinking of current from the output at only a small current sinking level. The initial sinking current level and the charge acceleration are constrained by the size and internal resistance of the small current carrying capacity transistor element. As a result the positive ground rise of potential proportional to di/dt is also constrained to a lower level, typically less than one half that of a conventional output buffer.
The separate pulldown delay resistance element and the parasitic capacitance of the primary pulldown transistor element form an RC delay network which delays turn on of the primary or large current carrying capacity pulldown transistor element. This delay is determined by the selected resistance value of the pulldown delay resistance element and consequent time constant of the RC delay network. An advantage of this arrangement according to U.S. Pat. No. 4,961,010 is that the small secondary sinking current continues to discharge the charge stored in the output load capacitance during the time constant delay. Upon turn on of the primary large current carrying capacity pulldown transistor element a second positive ground rise of potential occurs. However, the second ground bounce is now also limited by the reduction in charge in the output load capacitance already effected by the early small secondary sinking current. The reduced sinking current level and charge level also constrains and limits subsequent ground undershoot.
The Jeffrey B. Davis U.S. Pat. No. 4,961,010 describes noise reduction circuits for either an all CMOS transistor IC output buffer circuit or an all bipolar transistor IC output buffer circuit. Similarly the related Jeffrey B. Davis U.S. Pat. No. 5,036,222 issued Jul. 30, 1991 for OUTPUT BUFFER CIRCUIT WITH OUTPUT VOLTAGE SENSING FOR REDUCING SWITCHING INDUCED NOISE and the related Jeffrey B. Davis U.S. patent application Ser. No. 483,927 filed Feb. 22, 1990 for OUTPUT BUFFER CIRCUIT WITH SIGNAL FEED FORWARD FOR REDUCING SWITCHING INDUCED NOISE describe other noise reduction circuits for all CMOS transistor output buffer circuits. It is not apparent from these references how noise reduction may be achieved in the integrated BICMOS output buffer circuits with mixed CMOS transistors and bipolar transistors, for example as described in the related patent application.